1. Field of the Invention
Exemplary embodiments of the present invention relate to a non-volatile memory device.
2. Description of the Related Art
Non-volatile memory devices retain data stored therein although a power source has been cut off. Among the non-volatile memory devices, floating gate-type non-volatile memory devices, which are referred to as non-volatile memory devices hereafter, are usually used at present. A floating gate-type non-volatile memory device is disposed over a channel region of a substrate and it is driven by using a floating gate insulated from the channel region. In particular, the floating gate-type non-volatile memory device is driven as the threshold voltage of a memory cell shifts by controlling the amount of charges sustained in a conductive band of the floating gate.
A non-volatile memory device includes a memory cell array which stores data. The memory cell array includes a plurality of memory cell blocks. Each memory cell block includes a plurality of pages, and each page includes a plurality of memory cells. The memory cells are divided into on-cells and off-cells according to the distribution of threshold voltage. On-cells are erased cells and off-cells are programmed cells. The non-volatile memory device performs an erase operation on a memory block basis, and performs a write or read operation on a page basis.
Meanwhile, a non-volatile memory device may store one-bit data or data of more than two bits in one memory cell. Generally, a memory cell storing one-bit data is referred to as a single level cell (SLC) and a memory cell storing data of more than two bits is referred to as a multi-level cell (MLC). A single level cell has an erase state and a program state according to a threshold voltage. A multi-level cell has an erase state and a plurality of program states according to a threshold voltage.
As for a non-volatile memory device having multi-level cells, it is important to make the width of a threshold voltage distribution region narrow to secure a margin between program states. Generally, a memory cell of a non-volatile memory device having multi-level cells stores 2-bit data or 3-bit data. Herein, the performance and reliability of the non-volatile memory device having multi-level cells may be improved by setting the threshold voltage level of some of the program states and the erase state to a negative voltage level.
Meanwhile, a plurality of memory cells included in one block are coupled with a plurality of word lines through a plurality of high-voltage transistors. When the block is selected, the voltages of the word lines are transferred to a plurality of local lines coupled with the memory cells through the high-voltage transistors. When the block is not selected, the voltages of the word lines are cut off by the high-voltage transistors.
When the threshold voltages of the memory cells have a positive distribution, it is possible to transfer or cut off the voltages of the word lines just by applying a voltage higher than a ground voltage to the high-voltage transistors. However, as the threshold voltages of the memory cells include a negative distribution, it may not be possible to cut off the voltages of the word lines just by applying a voltage higher than a ground voltage to the high-voltage transistors.